1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor apparatus, in particular, a method of fabricating a stacked multi-chip package (stacked MCP) in which a plurality of semiconductor chips are stacked in one package.
2. Description of Related Art
Recently, with a need for higher performance and smaller electronic equipment, semiconductor apparatus have become more functional and smaller through development of multi-chip package in which a plurality of semiconductor chips are placed in one package. Moreover, there are two types of multi-chip package; a flat surface MCP in which a plurality of semiconductor chips are arranged on a flat surface, and a stacked MCP in which a plurality of semiconductor chips are stacked in the direction of thickness. Contribution of a flat surface MCP, in which semiconductor chips are arranged on a flat surface, to miniaturization of electronic equipment is small because it requires large mounting area. For this reason, development of stacked MCP in which semiconductor chips are stacked is emphasized more in recent years.
In the related art, a stacked MCP was fabricated by first dividing a semiconductor wafer, in which elements are integrated, into small semiconductor chips, which are then stacked together. However, in stacking semiconductor chips, determination of relative position of semiconductor chips stacked vertically is difficult, and positioning error easily occurs. In particular, in stacking semiconductors of the same size, confirmation of position of bottom semiconductor chip with naked eyes or video image is difficult, resulting in positioning error. For this reason, in mutually and electrically connecting semiconductor chips vertically for example, through small electrode parts provided in the semiconductor chip, positioning error of the electrode parts often occurs, resulting in connection failures.
The present invention aims to resolve shortcomings of aforementioned prior art by achieving accurate vertical stacking of semiconductor chips.
In order to achieve aforementioned aim of the present invention, a first method of fabricating a semiconductor apparatus of the present invention may consist of a step for providing pattern formation alignment marks on semiconductor wafers, a step for forming through-holes for stacking at a plurality of predetermined positions in each chip formation area of the semiconductor wafers using the alignment marks as reference, a step for forming a circuit on the semiconductor wafers with the through-holes, a step for dividing the wafers with circuit into a plurality of semiconductor chips, and a step for stacking a plurality of the divided semiconductor chips by matching the through-holes for stacking which are provided on each semiconductor chip.
As commonly known, elements and wiring (circuits) are formed on a semiconductor wafer, hence, various patterns are transcribed many times using an enlargement mask (reticule). Moreover, on a semiconductor wafer in general, an oxidation film is formed by heat oxidizing the entire semiconductor wafer, after which alignment marks for pattern formation are provided by etching and the like to prevent positioning error between patterns to be transcribed. Hence, using the pattern formation alignment marks as reference, a pair of through-holes for stacking is created on predetermined positions in a semiconductor wafer, namely a plurality of predetermined positions in areas where each semiconductor chips is formed such as diagonally opposite positions in a semiconductor chips. Then, in stacking the semiconductor chips which are formed by dividing semiconductor wafers with circuit, the semiconductor chips may be stacked accurately by matching the through-holes. For this reason, even when stacked semiconductor chips are to be connected electrically through electrode parts provided in the semiconductor chips, the positioning error of the electrode parts may be prevented and concerns for connection failure may be eliminated. Here, in stacking semiconductor chips, use of commonly known back-light method which illuminate the semiconductor chips from the bottom enables accurate identification of through-holes for stacking, making easier to match positions of through-holes.
Moreover, a second method of fabricating a semiconductor apparatus of the present invention may consist of a step for providing pattern formation alignment marks on semiconductor wafers, a step for forming through-holes for stacking at a plurality of predetermined positions in each chip formation area of the semiconductor wafers using the alignment marks as reference, a step for forming a circuit on the semiconductor wafers with the through-holes, a step for stacking a plurality of the semiconductor wafers by matching the through-holes for stacking which are provided on the semiconductor wafers, and a step for dividing the stacked semiconductor wafers in stacked condition, into a plurality of semiconductor chips.
In the second exemplary embodiment, semiconductor wafers are stacked, before dividing into semiconductor chips, by matching through-holes, then the stacked wafers are cut and divided into the size of semiconductor chips. Hence, accurate determination of mutual positions of stacked semiconductor chips is achieved just like the case of the first exemplary embodiment. Moreover, because semiconductor wafers are stacked before dividing, the number of through-holes for stacking being formed on the wafer may be reduced.
In the first and the second exemplary embodiments, the through-holes for stacking may be formed on the positions where electrode parts of the circuit being formed on the semiconductor wafers are provided. By providing through-holes on the electrode position in such manner, stacked semiconductor chips may easily be connected electrically by arranging metal such as copper and aluminum in the through-holes through electroless plating and spattering, or by filling the holes with conductive adhesive agent, which results in simplification of the process. Moreover, the elements in the wall surface of the through-holes are oxidized during the formation stage, which eliminates need for special insulation treatment of the through-holes.
Furthermore, the through-holes for stacking may be formed on the positions where the active surface and the non-active surface of the semiconductor wafers are electrically connected. In fact, when a front surface (active surface) and a back surface (non-active surface) of a semiconductor chip are electrically connected, such as in grounding, by forming through-holes for stacking at a position where a front surface and the back surface are connected electrically and by arranging conductive material in the through- holes after stacking by matching the through-holes, conductivity between front surface and the back surface of the semiconductor chip may be easily achieved in addition to the accurate stacking of semiconductor chips.
Moreover, a third exemplary embodiment of a method of fabricating a semiconductor apparatus of the present invention may consist of a step for forming a circuit on semiconductor wafers, a step for forming through-holes for stacking on a plurality of electrode parts in the circuit being formed on the semiconductor wafers, a step for stacking a plurality of the semiconductor wafers by matching the through-holes for stacking being provided in the semiconductor wafers and for mutually bonding stacked semiconductor wafers by injecting conductive adhesive agents inside the through-holes for stacking, and a step for dividing the plurality of bonded semiconductor wafers into the size of the semiconductor chips. In this exemplarly embodiment also, because of stacking by matching through-holes, the accuracy in stacking semiconductor chips may be improved. Moreover, injection of conductive adhesive agent into through-holes enables simultaneous execution of mutual bonding of semiconductor wafers and mutual electrical connection of semiconductor chips, resulting in process simplification.